low-voltage/low-power copyright ? 2011 by silicon laboratories 11.03.11 port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 128k byte isp flash program memory 256 byte sram sfr bus 8092 byte xram port 1 drivers p1.0/pc0 p1.1/pc1 p1.2/xtal3 p1.3/xtal4 p1.4 p1.5/int5 port 2 drivers p2.0/sck1 p2.1/miso1 p2.2/mosi1 p2.3/nss1 p2.4 spi 0 analog peripherals comparators + - vbat vbat vdc xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12-bit 75ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator vref gnd p1.6/int6 p1.7 cp0, cp0a p2.5 p2.6 p2.7 + - cp1, cp1a enhanced smartclock oscillator xtal3 xtal4 dc/dc buck converter ind gnddc vreg digital power crc engine p3-6 drivers p7 driver lcd charge pump aes engine dma cap p3.0...p6.7 p7.0/c2d 16 32 pulse counter lcd (up to 4x32) encoder emif gnd vdd analog power spi 1 (dma enabled) vbatdc c8051f96x ultra-low-power, high-efficiency, battery-powered metering mcu ultra-low power @ 3.6 v - 110 a/mhz, low-power active, dc-dc enabled - 110 na sleep current with data retention; por monitor enabled - 400 na sleep current with smartclock (internal lfo) - 700 na sleep current with smartclock (external xtal) - 2 s wake-up from any sleep mode 12-bit; 16 ch. analog to digital converter - up to 75 ksps, 12-bit mode or 300 ksps 10-bit mode - external pin or internal vref (no external capacitor required) - on-chip pga allows measuri ng voltages up to twice the ? reference voltage - autonomous burst mode with 16-bit automatic averaging ? accumulator - integrated temperature sensor two low current comparators - programmable hysteresis and response time - configurable as interrupt or reset source internal 6-bit current reference - up to 500 a; source and sink capability - enhanced resolution via pwm interpolation integrated lcd controller - supports up to 128 segments (32x4) - integrated charge pump for contrast control metering-specific peripherals - dc-dc buck converter allows dynamic voltage scaling for ? maximum efficiency (250 mw output) - sleep-mode pulse accumulator with programmable switch ? de-bounce and pull-up control interfaces directly to metering sensor - data packet processing engine (dppe) includes hardware aes, dma, crc, and encoding blocks for acceleration of wire - less protocols - manchester and three-out-of-six encoder hardware for power- efficient implementation of the wireless m-bus specification high-speed enhanced 8051 c core - pipe-lined instruction architecture executes 70% of instructions in 1 or 2 system clocks memory - up to 128 kb flash; in-system programmable; full read/write/ erase functionality over the entire supply range - up to 8 kb data retention ram digital peripherals - up to 57 port i/o; all 5 v tolerant with programmable drive strength - hardware enhanced uart, 2 spi and i 2 c serial ports available concurrently - four general-purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with six capture/com - pare/pwm modules and watchdog timer clock sources - precision internal oscillators: 24.5 mhz with 2% accuracy sup - ports uart operation; spread-spectrum mode for reduced emi - low power internal oscillator: 20 mhz - external oscillator: crystal, rc, c, cmos clock - smartclock oscillator: 32.768 khz crystal or 16.4 khz internal lfo with three independent alarms on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in- system debug (no emulator required) - provides four breakpoints, single stepping package options - 76-pin dqfn (6x6 mm), rohs compliant - 40-pin qfn (6x6 mm), rohs compliant - 80-pin qfp (12x12 mm), rohs compliant development kit: c8051f960dk supply voltage: 1.8 to 3.8 v temperature range: ?40 to +85 c
low-voltage/low-power copyright ? 2011 by silicon laboratories 11.03.11 silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned her ein are trademarks or registered tr ademarks of their respective holders c8051f96x ultra-low-power, high-efficiency, battery-powered metering mcu selected electrical specifications parameter symbol conditions min typ max units active mode current ibat vbat = 3.6 v, f = 20 mhz ? 110 ? ua/mhz active mode current ibat f = 20 mhz lfo; dc-dc enabled executing code from flash; pclkact = 0x00; vbat = 3.6 v ?2.2? ma sleep mode current idd sleep mode, smartclock running, internal lfo; 3.6 v ?0.4? ua sleep mode current idd sleep mode, smartclock running, 32.768 khz crystal; 3.6 v ?0.7? ua buck regulator efficiency 3.6 v input voltage ? 80 ? % lcd refresh current 1 internal lfo, lcd charge pump disabled; 60 hz; non-multiplexed operation (static mode); 3.6 v ?0.4? ua lcd refresh current 2 internal lfo, lcd charge pump disabled; 60 hz; multiplexed operation; 3.6 v ?0.8? ua supply input voltage vbat 1.8 3.6 3.8 v product family part number memory (flash/ram) i/o lcd package (mm) c8051f960-a-gm 128 kb / 8 kb 57 32x4 dqfn76 (6x6) c8051f960-a-gq 128 kb / 8 kb 57 32x4 qfp80 (12x12) c8051f961-a-gm 128 kb / 8 kb 34 9x4 qfn40 (6x6) c8051f962-a-gm 128 kb / 8 kb 57 ? dqfn76 (6x6) c8051f962-a-gq 128 kb / 8 kb 57 ? qfp80 (12x12) c8051f963-a-gm 128 kb / 8 kb 34 ? qfn40 (6x6) c8051f964-a-gm 64 kb / 8 kb 57 32x4 dqfn76 (6x6) c8051f964-a-gq 64 kb / 8 kb 57 32x4 qfp80 (12x12) c8051f965-a-gm 64 kb / 8 kb 34 9x4 qfn40 (6x6) c8051f966-a-gm 32 kb / 8 kb 57 32x4 dqfn76 (6x6) c8051f966-a-gq 32 kb / 8 kb 57 32x4 qfp80 (12x12) C8051F967-A-GM 32 kb / 8 kb 34 9x4 qfn40 (6x6) c8051f968-a-gm 16 kb / 4 kb 57 32x4 dqfn76 (6x6) c8051f968-a-gq 16 kb / 4 kb 57 32x4 qfp80 (12x12) c8051f969-a-gm 16 kb / 4 kb 34 9x4 qfn40 (6x6)
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